The present invention relates generally to interrupts in a computer system, and more specifically to a programmable interrupt controller (PIC) configuration for use in a multiprocessing environment.
A programmable interrupt controller (PIC) is a device for handling multi-level priority interrupts in a computer system. The PIC receives requests from peripheral devices requiring service, prioritizes the requests, and issues an interrupt to the CPU. For each type of interrupt there is typically an interrupt service routine that the CPU executes. When the CPU acknowledges the interrupt, the PIC provides a pointer (vector) to an address in a table so that the CPU can begin executing the appropriate service routine.
The Chips and Technologies 82C226 System Peripheral Chip provides a number of logic support functions and includes a PIC. The PIC includes sixteen incoming interrupt request lines to which are connected external devices capable of generating interrupts. Internal registers can be configured to mask out selected incoming interrupt requests. An interrupt request on one of these lines causes the PIC to assert a signal on its interrupt line to the CPU. Thereafter, the CPU initiates an interrupt acknowledge cycle on the system data bus, in response to which the PIC provides a vector for the highest priority interrupting device. The PICs can be cascaded to provide additional levels of interrupt.
The existing software base written for 8086, 8088, 80286 and 80386 microprocessors assumes that there is one CPU and one PIC (possibly cascaded). This assumption places a constraint on the design of prospective multiprocessor systems since commercial considerations dictate that existing software run on such systems.
One approach to extending to a multiprocessor environment while maintaining software compatibility is to use a master/slave configuration. In such a case, the PIC would send all interrupts to one of the CPUs, designated the master, and the system would include a mechanism, such as a set of radial attention lines and a set of message buffers, for the CPUs to communicate with each other. The master CPU, in response to an interrupt, would perform the initial vectoring, but the interrupt service routine could specify that some other CPU, referred to as a slave, should service the interrupt. The master CPU would then set the appropriate message buffer entries, and assert a signal on the slave CPU's attention line. The slave CPU would then look in the message buffer to find the starting address for servicing the interrupt.
Such a system presumably works, but suffers from the problem that the master CPU ends up spending a lot of time directing interrupts to slave CPU's. This problem can be acute in a heavy use environment of the type that dictates the use of a multiprocessor configuration in the first place. Additionally, the transfer of control from one processor to the other requires some amount of time, which lengthens the average response time for interrupts.